This invention relates to voltage regulators, and more particularly relates to methods for preventing overshoot in Miller compensated voltage regulators during enable.
Electronic circuits are increasingly used in portable and mobile applications in which low power consumption is highly desirable in order to avoid the necessity of large and bulky battery supplies. Such applications include wireless phones, personal pagers, personal digital assistants, etc.
One way of achieving such low power consumption is to provide a so-called Disable, or, Power Down, mode for the electronic circuit. Disable mode is provided as a general matter by including a module that monitors the use of the circuit and that signals the circuit to change from a normal mode to a disable mode when the circuit has not been called upon for use after a predetermined time period. This is frequently done by deactivating an enable signal for the circuit. In response, the circuit changes to a disabled state so that it consumes zero or the minimum power possible. When the module detects that the circuit is required for use again, the module signals the circuit to return to normal mode by reactivating the enable signal.
One circuit that finds frequent use in such applications is the Miller compensated voltage regulator. Such voltage regulators are considered desirable due to their flexible requirement regarding external filter capacitors. However, a problem arises in such regulators during the transition from disabled mode to enabled mode. This can be understood by reference to FIG. 1, which shows a circuit diagram of a prior art Miller compensated voltage regulator with enable/disable capability. Briefly, in the circuit of FIG. 1, an input differential pair of PMOS transistors MP1 and MP2 has current provided to their sources by current source 12 sourcing current ITAIL. Their drains are connected to a current mirror comprising NMOS transistors MN1 and MN2. A voltage reference VREF, such as a bandgap voltage, is provided to the gate of transistor MP2, while a feedback voltage VFB developed at the connection node FB of resistors R1 and R2, connected in series between the output node and ground, is provided to the gate of transistor MP1. The resulting voltage at the connection node between the drain of transistor MP2 and MN2, node NCC, is provided to the non-inverting input of an amplifier A2, which has a bias voltage VBIAS provided to its inverting input to control the magnitude of the output voltage VOUT at the output node OUT. The output of amplifier A2 controls the gate of a pass PMOS transistor MP3 connected between the power supply VDD and the output node. A filter capacitor CF, with its equivalent series resistance RF, is connected in parallel with a load, between the output node and ground. Miller compensation is provided by compensation capacitor CC connected between node OUT and node NCC.
Control of standby versus normal mode is provided by NMOS transistor MN3 connected by its source and drain between the source and drain, respectively, of transistor MN1, NMOS transistor MN4 connected by its source and drain between the source and drain, respectively, of transistor MN2, and by PMOS transistor MP4 connected by its source and drain between the source and gate, respectively, of transistor MP3. The inverse of the enable signal, {overscore (ENB)}, is provided to the gate of transistors MN3 and MN4, while the enable signal, ENB, is provided to the gate of transistor MP4. When ENB is low, and thus {overscore (ENB)} is high, the circuit is disabled. In this state, transistor MN3 turns off transistors MN1 and MN2 by shorting their gates to ground, transistor MN4 pulls node NCC to ground, and transistor MP4 turns off transistor MP3 and amplifier A2. Thus, the regulator circuit consumes, essentially, zero current. In addition, both nodes OUT and FB are grounded by resistors R1 and R2.
During the transition from disable to enable, when ENB is being brought high and {overscore (ENB)} is being brought low, transistors MN3, MN4 and MP4 are all being turned off, and amplifier A2 is being enabled. Due to the fact that the gate of transistor MP1 is already grounded by node VFB, all of the current ITAIL flows through transistors MP1 and MN1. Since transistors MN1 and MN2 are connected as a current mirror, this current through transistor MN1 is mirrored into transistor MN2, causing node NCC to be fully discharged by the current IMN2 through transistor MN2. As this occurs, amplifier A2 is overdriven and turns the pass device MP3 fully on, which pumps current ICF into the filter capacitor CF, as well as current ICC into compensation capacitor CC. The current ICF through CF determines the slew rate of the regulator output VOUT. The discharging current IMN2, along with capacitor CC, determines the slew rate of node NCC. Given the fact that VOUT is ramping up, NCC still ramps up, but at a slower slope due to the discharging current IMN2. Depending on the difference between these two rates, if by the time VOUT reaches the desired output level, VREG, but the voltage VNCC at node NCC is still lower than VBIAS, which means that amplifier A2 is still overdriven at the negative input, then VOUT will still keep rising until VNCC reaches VBIAS and shuts off the pass device transistor MP3. However, by then overshoot has already occurred, and the delay of the circuit response only makes it even worse. As a result, VNCC will go much higher than VBIAS, and the regulator will not settle back into its linear region until node OUT is discharged sufficiently so that VOUT has settled to the desired output level VREG.
This is shown in FIG. 4, which is a graph of voltage versus time, showing VOUT and VNCC, with the transition to enable beginning at time equal zero. As shown, at time t1 VOUT has reached VREG, as shown at 41, but VNCC, as shown at 42, is still below VBIAS. As a result, VOUT continues to rise above VREG until, at time t2 VNCC reaches VBIAS, as shown at 43. However, VNCC continues above VBIAS, since VOUT is above VREG. Eventually, however, both VOUT and VNCC settle toward their steady state voltages, VREG and VBIAS, respectively. Throughout the enable process, as described above, the desirable linear slew characteristic of the Miller effect never occurs, because amplifier A2 always saturates in either direction, the root reason being that Node NCC ramps up too slowly relative to node VOUT.
It would therefore be desirable to have a Miller compensated voltage regulator with enable/disable capability that avoids the problems described above.
As a general matter, the invention provides protection against overshoot as described above. This is done by controlling the initialization of an internal connection node of a Miller compensation capacitor so as to ensure that the Miller effect provides a linear slew rate at the output node. The rate of increase of the voltage at the internal node is controlled to as to rise to the level of a bias voltage, or to nearly the level of the bias voltage, before the output node reaches the desired output level.
According the invention there is provided a Miller compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage regulator includes a voltage regulation circuit responsive to a reference voltage at the input port to provide a regulated voltage at the output port. The voltage regulation circuit includes a first amplifier adapted to receive a reference voltage at a first input, having a second input, and having an output, and also a second amplifier having a first input coupled to an internal node, the internal node being coupled to the output of the first amplifier, the second amplifier having a second input adapted to receive a bias voltage and having an output. A pass transistor is provided having a source coupled to the voltage supply, having a drain coupled to the output port, and having a gate coupled to the output of the second amplifier, and a Miller compensation capacitor is provided coupled between the output port and the internal node. A feedback circuit is coupled between the output port and the second input of the first amplifier. In accordance with the invention, an enable control circuit is provided, adapted to maintain the internal node at a high impedance with respect to the voltage supply for a predetermined interval in response to a transition of an enable signal from signaling a disable mode to signaling an enable mode. This allows the voltage at the internal node to rise to the level of the bias voltage, or nearly so, before the voltage at the output port reaches the desired regulated level.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.